View QL3006_143910.PDF datasheet online --- IC-ON-LINE

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Two array clock/control networks available
6,000 Usable PLD Gates with 82 I/Os
Counters, 400 MHz Datapaths 0.35 m four-layer metal non-volatile CMOS process for smallest die sizes
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100% routable with 100% utilization and
to the logic cell flip-flop clock, set and reset inputs -- each driven by an input-only pin Two global clock/control networks available to the logic cell; F1, clock, set and reset inputs and the data input, I/O register clock, reset and enable inputs as well as the output enable control -- each driven by an inputonly or I/O pin, or any logic cell output or I/O cell feedback
complete pin-out stability Variable-grain logic cells provide high performance and 100% utilization Comprehensive design tools include high quality Verilog/VHDL synthesis
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Input + logic cell + output total delays
under 6 ns Data path speeds over 400 MHz Counter speeds over 300 MHz
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Interfaces with both 3.3 V and 5.0 V devices PCI compliant with 3.3 V and 5.0 V buses
for -1/-2/-3/-4 speed grades Full JTAG boundary scan I/O Cells with individually controlled Registered Input Path and Output Enables
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74 bidirectional input/output pins,
PCI-compliant for 5.0 V and 3.3 V buses for -1/-2/-3/-4 speed grades Four High Drive input-only pins Four High Drive input-only/distributed network pins
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The QL3006 is a 6,000 usable PLD gate member of the pASIC 3 family of FPGAs. pASIC 3 FPGAs are fabricated on a 0.35 m four-layer metal process using QuickLogic's patented ViaLink technology to provide a unique combination of high performance, high density, low cost, and extreme ease-of-use. The QL3006 contains 160 logic cells. With a maximum of 82 I/Os, the QL3006 is available in 68-pin PLCC, 84-pin PLCC, and 100-pin TQFP packages. Software support for the complete pASIC 3 family, including the QL3006, is available through three basic packages. The turnkey QuickWorks package provides the most complete FPGA software solution from design entry to logic synthesis, to place and route, to simulation. The QuickToolsTM for Workstations package provides a solution for designers who use Cadence, ExemplarTM, Mentor, Synopsys, Synplicity, ViewlogicTM, AldecTM, or other third-party tools for design entry, synthesis, or simulation.
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tPD tSU tH tCLK tCWHI tCWLO tSET tRESET tSW tRW
Combinatorial Delay Setup Time Hold Time Clock to Q Delay Clock High Time Clock Low Time Set Delay Reset Delay Set Width Reset Width
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High Drive Input Delay High Drive Input, Inverting Delay Input Register Set-Up Time Input Register Hold Time Input Register Clock To Q Input Register Reset Delay Input Register clock Enable Set-Up Time Input Register Clock Enable Hold Time
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Output Delay Low to High Output Delay High to Low Output Delay Tri-state to High Output Delay Tri-state to Low Output Delay High to Tri-State Output Delay Low to Tri-State
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The DC specifications are provided in 7DEOH through 7DEOH .
7DEOH $EVROXWH 0D[LPXP 5DWLQJV 3DUDPHWHU VCC Voltage VCCIO Voltage Input Voltage Latch-up Immunity 9DOXH -0.5 V to 4.6 V -0.5 V to 7.0 V -0.5 V to VCCIO +0.5 V 200 mA 3DUDPHWHU DC Input Current ESD Pad Protection Storage Temperature Lead Temperature 9DOXH 20 mA 2000 V -65C to +150C 300C
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Output LOW Voltage I or I/O Input Leakage Current 3-State Output Leakage Current Input Capacitance
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Output Short Circuit Currentc D.C. Supply Currentd D.C. Supply Current on VCCIO
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Voltage Factor vs. Supply Voltage
1.1000 1.0800 1.0600 1.0400
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Supply Voltage (V)
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Temperature Factor vs. Operating Temperature
1.15 1.10 1.05 1.00 0.95 0.90 0.85 -60 -40 -20 0 20 40 60 80
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Junction Temperature C
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400 us
Time
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The following requirements must be met when powering up the device (see )LJXUH ). QuickLogic recommends the following for the lowest possible power-up current. Not following these recommendations will cause the device to draw more current during power-up:
* When ramping up the power supplies keep (VCCIO -VCC)MAX 500 mV. * VCCIO must lead VCC when ramping the device. The power supply must take greater than or equal to 400 s to reach VCC. Ramping to VCC/VCCIO earlier than 400 s can cause the device to behave improperly.
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Instruction Register
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Mux Boundary-Scan Register (Data Register)
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I/O Registers
User Defined Data Register
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Microprocessors and Application Specific Integrated Circuits (ASICs) pose many design challenges, not the least of which concerns the accessibility of test points. The Joint Test Access Group (JTAG) formed in response to this challenge, resulting in IEEE standard 1149.1, the Standard Test Access Port and Boundary Scan Architecture. The JTAG boundary scan test methodology allows complete observation and control of the boundary pins of a JTAG-compatible device through JTAG software. A Test Access Port (TAP) controller works in concert with the Instruction Register (IR); these allow users to run three required tests, along with several user-defined tests. JTAG tests allow users to reduce system debug time, reuse test platforms and tools, and reuse subsystem tests for fuller verification of higher level system elements.
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* Extest Instruction. The Extest instruction performs a PCB interconnect test. This test
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places a device into an external boundary test mode, selecting the boundary scan register to be connected between the TAP's Test Data In (TDI) and Test Data Out (TDO) pins. Boundary scan cells are preloaded with test patterns (via the Sample/Preload Instruction), and input boundary cells capture the input data for analysis. * Sample/Preload Instruction. This instruction allows a device to remain in its functional mode, while selecting the boundary scan register to be connected between the TDI and TDO pins. For this test, the boundary scan register can be accessed via a data scan operation, allowing users to sample the functional data entering and leaving the device. * Bypass Instruction. The Bypass instruction allows data to skip a device's boundary scan entirely, so the data passes through the bypass register. The Bypass instruction allows users to test a device without passing through other devices. The bypass register is connected between the TDI and TDO pins, allowing serial data to be transferred through a device without affecting the operation of the device.
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)XQFWLRQ Test Data In for JTAG Active low Reset for JTAG Test Mode Select for JTAG Test Clock for JTAG Test data out for JTAG Special Test Mode
'HVFULSWLRQ Hold HIGH during normal operation. Connect to VCC if not used for JTAG. Hold LOW during normal operation. Connect to ground if not used for JTAG. Hold HIGH during normal operation. Connect to VCC if not used for JTAG. Hold HIGH or LOW during normal operation. Connect to VCC or ground if not used for JTAG. Output that must be left unconnected if not used for JTAG. Must be grounded during normal operation.
TDO STM I/ACLK I/GCLK I I/O VCC VCCIO GND
High-drive input and/or array Can be configured as either or both. network driver High-drive input and/or global Can be configured as either or both. network driver High-drive input Input/Output pin Power supply pin Input voltage tolerance pin Ground pin Use for input signals with high fanout. Can be configured as an input and/or output. Connect to 3.3 V supply. Connect to 5.0 V supply if 5 V input tolerance is required, otherwise connect to 3.3 V supply. Connect to ground.
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QL 3006 - 1 PF100 C QuickLogic device pASIC 3 device part number Speed Grade 0 = Quick 1 = Fast 2 = Faster 3 = Faster *4 = Wow Operating Range C = Commercial I = Industrial M = Military Package Code PL68=68-pin PLCC PL84 = 84-pin PLCC PF100 = 100-pin TQFP
* Contact QuickLogic regarding availability (see &RQWDFW ,QIRUPDWLRQ)
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Telephone: 408 990 4000 (US) 416 497 8884 (Canada) 44 1932 57 9011 (Europe) 49 89 930 86 170 (Germany) 852 8106 9091 (Asia) 81 45 470 5525 (Japan) E-mail:
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info@quicklogic.com support@quicklogic.com http://www.quicklogic.com/
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Copyright (c) 2003 QuickLogic Corporation. All Rights Reserved. The information contained in this document and the accompanying software programs is protected by copyright. All rights are reserved by QuickLogic Corporation. QuickLogic Corporation reserves the right to modify this document without any obligation to notify any person or entity of such revision. Copying, duplicating, selling, or otherwise distributing any part of this product without the prior written consent of an authorized representative of QuickLogic is prohibited. QuickLogic and the QuickLogic logo, pASIC, ViaLink, DeskFab, and QuickWorks are registered trademarks of QuickLogic Corporation; Eclipse, QuickFC, QuickDSP, QuickDR, QuickSD, QuickTools, QuickCore, QuickPro, SpDE, WebASIC, and WebESP are trademarks of QuickLogic Corporation.
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